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Some considerations in the design of high speed printed circuit board (PCB).

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Some considerations in the design of high speed printed circuit board (PCB).

Release date:2018-03-26 Author: admin Click:

The design considerations for high speed system PCB related to the application of SERDES are as follows:

(1) Microstrip and Stripline wiring.

The microstrip line is the wiring in the outer layer of the reference plane (GND or Vcc) separated by the dielectric media, which minimizes the delay. The ribbon line is wired between two reference planes (GND or Vcc), so that it can gain a greater tolerance, easier to control the impedance, and make the signal cleaner, as shown in the figure.

Some considerations in the design of high speed printed circuit board (PCB).

Microstrip line and ribbon line best wiring.

(2) high-speed differential signal to wiring.

High speed differential signal is Edge for wiring methods coupling (Edge) Coupled microstrip Coupled stripline (top), Edge (embedded signal layer, suitable for cloth high-speed SERDES difference signal to) and Broadside Coupled microstrip, as shown.

Some considerations in the design of high speed printed circuit board (PCB).

High-speed differential signal to wiring.

(3) by-pass capacitance (BypassCapacitor).

The by-pass capacitance is a small capacitor with very low series impedance, which is mainly used to filter the high frequency interference in the high-speed transform signal. In the FPGA system, there are three main bypass capacitors: the high speed system (100MHz~1GHz) is commonly used in the bypass capacitance range of 0.01nF to 10nF, which is generally within 1cm of the Vcc. Medium speed system (10 MHZ 100MHz), commonly used by the bypass capacitance range of 47nF to 100nF tantalum capacitors, generally within the Vcc 3cm; Low speed system (less than 10 megahertz), the commonly used bypass capacitance range is 470nF to 3300nF capacitance, and the layout of PCB is relatively free.

Some considerations in the design of high speed printed circuit board (PCB).

(4) optimal wiring of capacitance.

Capacitance wiring can follow the following design guidelines, as shown in the figure.

Some considerations in the design of high speed printed circuit board (PCB).

Capacitance best wiring.

Use large size through hole (Via) to connect capacitive pin pads to reduce coupling reactance.

Use a short, wide line to connect the solder to the hole and the capacitive pin, or directly connect the capacitive pin to the hole.

Use the LESR capacitance (Low Effective Series Resistance).

Each GND pin or hole should be connected to the ground plane.

(5) key points of high-speed system clock wiring.

Avoid using the serrated winding, and the clock wiring should be as straight as possible.

As far as possible in single signal layer wiring.

Try not to use holes as much as possible, because the holes will bring strong reflections and impedance mismatches.

Use microstrip wiring as far as possible to avoid using holes and minimize signal delay.

The ground plane is placed next to the clock signal layer to reduce noise and crosstalk. If the internal signal layer is used, the clock signal layer can be sandwiched between two ground planes to reduce noise and interference. Shorten the signal delay.

The clock signal should match the correct impedance.

(6) high-speed system coupling and wiring precautions.

Notice the impedance matching of the differential signal.

Pay attention to the width of the differential signal line so that it can tolerate 20% of the signal up or down time.

With the appropriate connector, the rated frequency of the connector should be able to meet the maximum design frequency.

The difference signal is coupled to the best possible use of the edge-couple method, avoiding the use of broadside-couple coupling, using the 3S rule, and avoiding coupling or crosstalk.

(7) high speed system noise filtering considerations.

Reduce the low frequency interference caused by power noise (below 1KHz), and add shielding or filter circuit at each power access end.

Add 100F electrolytic capacitor filter to each power source into PCB.

In order to reduce the high frequency noise, the coupling capacitance is arranged as much as possible at each Vcc and GND.

The Vcc and GND planes are arranged in parallel and separated by dielectric (such as fr-4pcb), and the bypass capacitors are arranged in other layers.

(8) Ground Bounce

Try to add the coupling capacitance to each Vcc/GND signal.

External Buffer is added at the output end of the counter and other high speed flip signals to reduce the drive capacity requirement.

The user I/O is set to output as a low level output signal, which corresponds to the virtual GND, which connects these low-level outputs to the ground plane.

For speed requirement is demanding the output signal is set to missile Slew (low rising slope) model.

Control load tolerance.

Reduce the signal that the clock is turning over and over, or distribute the signal as evenly as possible around the chip.

The frequency of the overturning signal is as close to the GND pin as possible.

When designing synchronous sequential circuits, the output should be avoided as far as possible.

The power supply and the ground diversion are arranged, so that can play the role of the overall upper and the inductance.

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